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this is information on a product in full production. april 2012 doc id 18093 rev 2 1/22 22 54AC164245 rad-hard 16-bit transceiver, 3.3 v to 5 v bidirectional level shifter datasheet ? production data features fully compatible with 54acs164245 dual supply bidirectional level shifter extended voltage range from 2.3 v to 5.5 v separated enable pin for 3-state output schmidt-triggered i/os: 100 mv hysteresis internal 26 limiting resistor on each i/o high speed: tpd = 8 ns maximum bus hold fail safe cold spare hermetic package 100 krad (si) at any mil1019 dose rate sel immune to 110mev.cm 2 /mg let ions rha qml-v qualified description the 54AC164245 is a rad-hard advanced high- speed cmos, schmitt trigger 16-bit bidirectional multi-purpose transceiver with 3-state outputs and cold sparing. designed for use as an interface between a 5 v bus and a 3.3 v bus in mixed 5 v/3.3 v supply systems, it achieves high-speed operation while maintaining the cmos low-power dissipation. all pins have cold spare buffers to change them to high impedance when v dd is tied to ground. this ic is intended for two-way asynchronous communication between the data buses and the direction of the data transmission is determined by the ndir inputs. the a port interfaces with the 3.3 v bus but can also operate at 2.3 v. the b port operates with the 5 v bus. note: contact your st sales office for information on the specific conditions for products in die form. ceramic flat-48 the upper metallic lid is not electrically connected to any pins, nor to the ic die inside the package table 1. device summary reference smd pin quality level package lead finish mass eppl temp range rhrac164245k1 - engineering model flat-48 gold 1.50 g - -55 c to +125 c rhrac164245k01v 5962r9858008vyc qmlv- flight gold target www.st.com
functional description 54AC164245 2/22 doc id 18093 rev 2 1 functional description figure 1. logic diagram 6port 6port 6port 6port !- $)2 ! ! ! ! ! ! ! ! " " " " " " " " ! ! ! ! ! ! ! ! " " " " " " " " $)2 /% /% table 2. function table enable, oex direction, dirx operation l l b data to a bus l h a data to b bus hx isolation
54AC164245 functional description doc id 18093 rev 2 3/22 1.1 cold spare the 54AC164245 features a co ld spare input and output buffers. in high reliability applications, cold sparing enables a redundant device to be tied to the data bus with its power supply at 0 v (v dd = v ss , v dd - v ss = 0 v) without affecting the bus signals or injecting current from the i/os to the power supplies. cold sparing also allows to keep unpowered redundant devices so that they can be switched on only when required. power consumption is therefore reduced by switching off the redundant circuit. this has no impact on the application. cold spare is achieved by implementing a high impedance between i/os and v dd . the esd protection is ensured through a non-conventional dedicated structure. 1.2 power-up during power up, all outputs are forced to high impedance. the high-impedance state is maintained approximately until v dd is high, thus avoiding any transient and erroneous signals during power-up. 1.3 pin connections figure 2. pin connections !-v
functional description 54AC164245 4/22 doc id 18093 rev 2 table 3. pin descriptions pin n symbol name and function 1 dir1 direction control inputs 2, 3, 5, 6, 8, 9, 11, 12 1b1 to 1b8 side b inputs or 3-state outputs (5 v port) 4,10, 15, 21, 28, 34, 39, 45 v ss reference voltage to ground 7, 18 v dd1 supply voltage (5 v) 13, 14, 16, 17, 19, 20, 22, 23 2b1 to 2b8 side b inputs or 3-state outputs (5 v port) 24 dir2 direction control inputs 25 ng2 output enable inputs (active low) 31, 42 v dd2 supply voltage (3.3 v) 47, 46, 44, 43, 41, 40, 38, 37 1a1 to 1a8 side a inputs or 3-state outputs (3.3 v port) 36, 35, 33, 32, 30, 29, 27, 26 2a1 to 2a8 side a inputs or 3-state outputs (3.3 v port) 48 ng1 output enable inputs (active low)
54AC164245 absolute maximum ra tings and operating conditions doc id 18093 rev 2 5/22 2 absolute maximum ratings and operating conditions absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 4. absolute maximum ratings (1) (2) (3) 1. stresses above the absolute maximum rating ma y cause permanent damage to the device. extended operation at the maximum levels may degrade performance and a ffect reliability. 2. unless otherwise noted, all voltages are referenced to v ss . 3. the limits for the parameters specified her ein shall apply over the full specified v dd range and case temperature range of -55c to +125c. symbol parameter value unit v dd1 5 v supply voltage (4) 4. v dd1 (5 v) may remain disconnected. -0.3 to +6.0 v v dd2 3 v supply voltage -0.3 to +6.0 v v ia dc input voltage range port a -0.3 to v dd1 +0.3 v v v ib dc input voltage range port b -0.3 to v dd1 +0.3 v v v oa dc output voltage range port a -0.3 to v dd1 +0.3 v v v ob dc output voltage range port b -0.3 to v dd1 +0.3 v v i ia dc input currents port a, anyone input 10 ma i ib dc input currents port b, anyone input 10 ma t stg storage temperature range -65 to +150 c t l lead temperature (10 sec) 300 c t j junction temperature range 175 c r thja thermal resistance junction to ambient (5) flat package, 48 pins 5. short-circuits can c ause excessive heating and destructive dissipation. val ues are typical. tbd c/w r thjc thermal resistance junction to case (5) flat package, 48 pins tbd c/w esd hbm: human body model (6) 6. human body model: a 100 pf capacit or is charged to the specified voltage, then discharged through a 1.5 k resistor between two pins of the device. this is done for all couples of connected pin combinations while the other pins are floating. 2kv
absolute maximum ratings and operating conditions 54AC164245 6/22 doc id 18093 rev 2 table 5. operating conditions (1) 1. unless otherwise noted, all voltages are referenced to v ss . symbol parameter value unit v dd1 supply voltage 4.5 to 5.5 or 2.3 to 3.6 v v dd2 supply voltage 2.3 to 3.6 or 4.5 to 5.5 v v i input voltage 0 to v dd1 v v o output voltage 0 to v dd1 v t op operating temperature -55 to +125 c d t / d v input rise and fall time v cc = 3.0, 4.5 or 5.5 (2) 2. derate system propagation delays by differenc e in rise time to switch point for t r or t f > 1 ns/v. 0 to 8 ns / v
54AC164245 electrical characteristics doc id 18093 rev 2 7/22 3 electrical characteristics t op = -55c to +125c, v dd1 = 4.5 v to 5.5 v, v dd2 = 2.7 v to 3.6 v, unless otherwise specified. table 6. dc specifications (1) symbol parameter port voltage test condition (v dd ) (2) limits unit min. max. v t+ schmitt trigger positive going threshold port a 3.3 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v 0.7 v dd2 v 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 4.5 and 5.5 v 0.7 v dd2 schmitt trigger positive going threshold port b 3.3 v v dd2 = 2.7 and 3.6 v v dd1 = 2.7 and 3.6 v 0.7 v dd1 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v 0.7 v dd1 v t- schmitt trigger positive going threshold port a 3.3 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v 0.3 v dd2 v 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 4.5 and 5.5 v 0.3 v dd2 schmitt trigger positive going threshold port b 3.3 v v dd1 = 2.7 and 3.6 v v dd2 = 2.7 and 3.6 v 0.3 v dd1 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v 0.3 v dd1 v h schmitt trigger range of hysteresis port a 3.3 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v 0.4 v 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 4.5 and 5.5 v 0.6 schmitt trigger range of hysteresis port b 3.3 v v dd1 = 2.7 and 3.6 v v dd2 = 2.7 and 3.6 v 0.4 5.0 v v dd1 = 4.5 and 5.5 v v dd2 = 2.7 and 3.6 v 0.6 i ih input current high port a (for input under test v i = v dd2 other inputs, v i = v dd2 or v ss ) 3.3 v v dd1 = 5.5 v v dd2 = 3.6 v 3 a 5.0 v v dd1 = 5.5 v v dd2 = 5.5 v 3 input current high port b (for input under test v i = v dd1 other inputs, v i = v dd1 or v ss ) 3.3 v v dd1 = 3.6 v v dd2 = 3.6 v 3 5.0 v v dd1 = 5.5 v v dd2 = 3.6 v 3
electrical characteristics 54AC164245 8/22 doc id 18093 rev 2 i il input current low port a (for input under test v i =v ss other inputs, v i = v dd2 or v ss 3.3 v v dd1 = 5.5 v v dd2 = 3.6 v -1 a 5 v v dd1 = 5.5 v v dd2 = 5.5 v -1 input current low port b (for input under test v i =v ss other inputs, v i = v dd1 or v ss 3.3 v v dd1 = 3.6 v v dd2 = 3.6 v -1 5 v v dd1 = 5.5 v v dd2 = 3.6 v -1 i cs input current cold spare mode port a = port b = 5.5 v = v i dirn = 5.5 v, oen = 5.5 v v dd1 = 0 v -1 5 a input current cold spare mode port a = port b = 5.5 v = v i dirn = 0v, oen = 5.5 v v dd1 = 0 v -1 5 input current cold spare mode port a = port b = 5.5 v = v i dirn = 5.5 v, oen = 0 v v dd1 = 0 v -1 5 input current cold spare mode port a = port b = 5.5 v = v i dirn = 0 v , oen = 0 v v dd1 = 0 v -1 5 v ol1 low level output voltage port a, i ol = 8 ma for all inputs affecting output under test, v i = v dd2 or v ss 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v 0.5 v 5 v v dd1 = 4.5 v v dd2 = 4.5 v 0.4 low level output voltage port b, i ol = 8 ma for all inputs affecting output under test, v i = v dd1 or v ss 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v 0.5 5 v v dd1 = 4.5 v v dd2 = 2.7 v 0.4 v ol2 low level output voltage 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v 0.2 v port a, i ol = 100 a for all inputs affecting output under test, v i = v dd2 or v ss 5 v v dd1 = 4.5 v v dd2 = 4.5 v 0.2 low level output voltage 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v 0.2 port b, i ol = 100 a for all inputs affecting output under test, v i =v dd1 or v ss 5 v v dd1 = 4.5 v v dd2 = 2.7 v 0.2 table 6. dc specifications (1) (continued) symbol parameter port voltage test condition (v dd ) (2) limits unit min. max.
54AC164245 electrical characteristics doc id 18093 rev 2 9/22 v oh1 high level output voltage port a, i oh = -8 ma for all inputs affecting output under test , v i = v dd2 or v ss 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v v dd2 -0.9 v 5 v v dd1 = 4.5 v v dd2 = 4.5 v v dd2 -0.7 high level output voltage port b , i oh = -8 ma for all inputs affecting output under test, v i = v dd1 or v ss 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v v dd1 -0.9 5 v v dd1 = 4.5 v v dd2 = 2.7 v v dd1 -0.7 v oh2 high level output voltage port a, i oh = - 100 a for all inputs affecting output under test, v i = v dd2 or v ss 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v v dd2 -0.2 5 v v dd1 = 4.5 v v dd2 = 4.5 v v dd2 -0.2 high level output voltage port b , i oh = - 100 a for all inputs affecting output under test, v i = v dd1 or v ss 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v v dd1 -0.2 5 v v dd1 = 4.5 v v dd2 = 2.7 v v dd1 -0.2 i ol (3) output current (sink) port a, v i = v ss 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v v ol = 0.5 v 8.0 ma 5 v v dd1 = 4.5 v v dd2 = 4.5 v v ol = 0.4 v 8.0 output current (sink) port b, v i = v ss 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v v ol = 0.5 v 8.0 5 v v dd1 = 4.5 v v dd2 = 2.7 v v ol = 0.4 v 8.0 table 6. dc specifications (1) (continued) symbol parameter port voltage test condition (v dd ) (2) limits unit min. max.
electrical characteristics 54AC164245 10/22 doc id 18093 rev 2 i oh (4) output current (source) port a, v i = v dd2 or v ss 3.3 v v dd1 = 4.5 v v dd2 = 2.7 v v oh = v dd2 -0.9 v -8.0 ma 5 v v dd1 = 4.5 v v dd2 = 4.5 v v oh = v dd2 -0.7 v -8.0 output current (source) port b, v i = v dd2 or v ss 3.3 v v dd1 = 2.7 v v dd2 = 2.7 v v oh = v dd2 -0.9 v -8.0 5 v v dd1 = 4.5 v v dd2 = 2.7 v v oh = v dd2 - 0.7 v -8.0 i ozh three-state output leakage current high port a, for input under test, v i = v dd2 other inputs, v o = v dd2 v i =v dd2 or v ss 3.3 v v dd1 = 5.5 v v dd2 = 3.6 v 3.0 a v dd1 = 5.5 v v dd2 = 5.5 v 3.0 three-state output leakage current high port b, for input under test, v i = v dd1 other inputs, v o = v dd1 v i = v dd1 or v ss 3.3 v v dd1 = 3.6 v v dd2 = 3.6 v 3.0 5 v v dd1 = 5.5 v v dd2 = 3.6 v 3.0 i ozl three-state output leakage current low port a, for input under test, v i = v ss other inputs, v o = v ss v i = v dd2 or v ss 3.3 v v dd1 = 5.5 v v dd2 = 3.6 v -1.0 a 5 v v dd1 = 5.5 v v dd2 = 5.5 v -1.0 three-state output leakage current low port b, for input under test , v i = v ss other inputs, v o = v ss v i = v dd1 or v ss 3.3 v v dd1 = 3.6 v v dd2 = 3.6 v -1.0 5 v v dd1 = 5.5 v v dd2 = 3.6 v -1.0 i os (3) (4) short circuit output current port a, v o = v dd2 or v ss 3.3 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v -100 100 ma 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v -200 200 short circuit output current port b, v o = v dd1 or v ss 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.6 v -100 100 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v -200 200 table 6. dc specifications (1) (continued) symbol parameter port voltage test condition (v dd ) (2) limits unit min. max.
54AC164245 electrical characteristics doc id 18093 rev 2 11/22 p d (3) (5) (6) power dissipation, port a, c l = 50 pf per switching output 3.3 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 1.5 mw/ mhz 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 2.0 power dissipation, port b, c l = 50 pf per switching output 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.6 v 1.5 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 2.0 i ddq quiescent supply current port a, v i = v dd2 or v ss 5 v v dd1 = 5.5 v v dd2 = 5.5 v at 25c 10 a v dd1 = 5.5 v v dd2 = 5.5 v at -55 to +125c 100 quiescent supply current port b, v i = v dd1 or v ss 5 v v dd1 = 5.5 v v dd2 = 5.5 v at 25c 10 v dd1 = 5.5 v v dd2 = 5.5 v at -55 to +125c 100 c i input capacitance f = 1 mhz v dd1 = v dd2 = 0 v 15 pf c o output capacitance f = 1 mhz v dd1 = v dd2 = 0 v 15 pf (7) functional test v ih = 0.7 v dd , v il = 0.3 v dd v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v l h 1. each input/output, as applicable, is tested at the specified te mperature, for the specified li mits, to the tests specified in smd5962-98580 table i. non-designated output terminals are high level logic, low level logic or open, except for all i dd tests, where the output terminals are open. when performing thes e tests, the current meter must be placed in the circuit such that all current flows through the meter. 2. this device requires both vdd1 and vdd2 power supplies fo r operation. the power supply is indicated and followed by the voltage to which the power supply is set to the given test. 3. this parameter is supplied as a des ign limit but not guaranteed or tested. 4. no more than one output should be shorted at a time for a maximum duration of one second. 5. power does not include power contributi on of any cmos output sink current. 6. power dissipation specified per switching output. 7. tests must be performed in sequence, attributes data only. f unctional tests shall include the truth table and other logic patterns used for fault detection. the test vectors used to verify the truth table must, at minimum, test all the functions of each input and output. all possible input to output logic patte rns per function shall be guaranteed, if not tested, to the function table, ta b l e 2 . functional tests are performed in sequence as approved by the qualifying activity on qualified devices. functional tests are conducted in accordance with mil-std-883 wi th the following input test conditions: vih = v ih (min + 20%, -0%); v il = v il (max + 0%, -50%), as specified herein, fo r ttl, cmos, or schmitt compatible inputs. devices are guaranteed to v ih(min) and v il(max) . table 6. dc specifications (1) (continued) symbol parameter port voltage test condition (v dd ) (2) limits unit min. max.
electrical characteristics 54AC164245 12/22 doc id 18093 rev 2 table 7. ac electrical characteristics (1) symbol parameter port vo ltage test condition (v dd ) limits unit min. max. t plh propagation delay time, data to bus (active low) c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 =2.7 to 3.6 v 1.0 20 ns propagation delay time, data to bus (active low) c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.6 v v dd2 = 2.7 to 3.6 v 1.0 20 port a = port b = 5 v v dd1 =4.5 to 5.5 v v dd2 =4.5 to 5.5 v 1.0 15 t phl propagation delay time, data to bus (active high) c l = 50 pf port a = 3.3v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 1.0 20 ns propagation delay time, data to bus (active high) c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.6 v v dd2 = 2.7 to 3.6 v 1.0 20 port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 1.0 15 t pzl propagation delay time, output enable, oen to bus (active low), c l = 50 pf port a = 3.3 v port b = 5v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 1.0 18 ns propagation delay time, output enable, oen to bus (active low), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.6 v v dd2 = 2.7 to 3.6 v 1.0 18 port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 1.0 12 t pzh propagation delay time, output enable, oen to bus (active high), c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 1.0 18 ns propagation delay time, output enable, oen to bus (active high), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.6 v v dd2 = 2.7 to 3.6 v 1.0 18 port a = port b = 5 v v dd1 = 4.5 to 5.5v v dd2 = 4.5 to 5.5v 1.0 12 t plz propagation delay time, output disable, oen to bus (low impedance), c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.6 v 1.0 20 ns propagation delay time, output disable, oen to bus (low impedance), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.6 v v dd2 = 2.7 to 3.6 v 1.0 20 port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 1.0 15 t phz propagation delay time, output disable, oen to bus (high impedance), c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.3 v 1.0 18 ns propagation delay time, output disable, oen to bus (high impedance), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.3 v 1.0 18 port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 1.0 12
54AC164245 electrical characteristics doc id 18093 rev 2 13/22 t pzl (1) propagation delay time, output enable, dirn to bus (active low), c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.3 v 1.0 18 ns propagation delay time, output enable, dirn to bus (active low), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.3 v 1.0 18 port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 1.0 12 t pzh (1) propagation delay time, output enable, dirn to bus (active high), c l = 50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.3 v 1.0 18 ns propagation delay time, output enable, dirn to bus (active high), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.3 v 1.0 18 port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 1.0 12 t plz (1) propagation delay time, output disable, dirn to bus (low impedance), c l =50 pf port a = 3.3 v port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.3 v 1.0 20 ns propagation delay time, output disable, dirn to bus (low impedance), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.3 v 1.0 20 port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 1.0 15 t phz (1) propagation delay time, output disable, dirn to bus (high impedance), c l = 50 pf port a = 3.3 v port b = 5.0 v v dd1 = 4.5 to 5.5 v v dd2 = 2.7 to 3.3 v 1.0 20 ns propagation delay time, output disable, dirn to bus (high impedance), c l = 50 pf port a = port b = 3.3 v v dd1 = 2.7 to 3.3 v v dd2 = 2.7 to 3.3 v 1.0 20 port a = port b = 5 v v dd1 = 4.5 to 5.5 v v dd2 = 4.5 to 5.5 v 1.0 15 1. guaranteed by design but not tested. table 7. ac electrical characteristics (1) (continued) symbol parameter port vo ltage test condition (v dd ) limits unit min. max.
radiations 54AC164245 14/22 doc id 18093 rev 2 4 radiations total dose (mil1019 dose rate): all parameters are post-irradiation guaranteed by wafer-lot acceptance (after dose, all guaranteed electrical parameters are tested on a sample of units of each wafer lot). all parameters provided in ta b l e 6 and ta bl e 7 apply to both pre- and post-irradiation. the 54AC164245 is a pure cmos product. the irradiation is performed at high dose rates. heavy ions: the behavior of the product when submitted to heavy ions is guaranteed by qualification and is not tested in production. heavy-ion trials are performed on qualification lots only. table 8. radiations type features value unit tid total ionizing dose high dose rate (50 - 300 rad/sec) up to: 100 k rad heavy ions sel immune (at 125c) up to: 110 mev.cm2/mg seu immune up to: 64
54AC164245 test circuit doc id 18093 rev 2 15/22 5 test circuit figure 3. test circuit note: c l = 50 pf or equivalent (includes jig and probe capacitance), r t = z out of pulse generator (typically 50 ), v ref = 0.5 v dd . i src is set to -1.0 ma and i snk is set to 1.0 ma for t phl and t plh measurements. input signal from pulse generator: v i = 0.0 v to v dd ; f = 10 mhz; t r = 1.0 v/ns "0.3 v/ns; t f = 1.0 v/ns "0.3 v/ns; tr and tf are measured from 0.1 v dd to 0.9 v dd and from 0.9 v dd to 0.1 v dd respectively. figure 4. waveform 1: propagation delay !-v 05,3% '%.%2!4/2 $54 6 ## ) 3.+ 6 2%& 2 4 # , $ $ $ $ ) 32# !-v ).054 /54054 t r t f t 0(, t 0,( 6 $$ '.$ 6 /( 6 /,
test circuit 54AC164245 16/22 doc id 18093 rev 2 figure 5. waveform 2: enable and disable times (port a = port b, 5 v operation) figure 6. waveform 3: enable and disable times (port a = port b, 3.3 v operation) !-v ).054 /54054 t 0:( t 0:, 6 $$ 6 $$ 6 /54054 t 0,: t 0(: 6 $$ 6 6 $$ 6 $$ 6 $$ 6 $$ 6 $$ 6 6 $$ !-v ).054 /54054 t 0:( t 0:, 6 $$ 6 $$ 6 /54054 t 0,: t 0(: 6 $$ 6 6 $$ 6 $$ 6 $$ 6 $$ 6 $$ 6 6 $$
54AC164245 test circuit doc id 18093 rev 2 17/22 figure 7. waveform 4: enable and disable times (port a = 3.3 v, port b = 5 v) !-v ).054 /54054 t 0:( t 0:, 6 $$ 6 $$ 6 /54054 t 0,: t 0(: 6 $$ 6 6 $$ 6 $$ 6 $$ 6 $$ 6 $$ 6 6 $$ /54054 t 0:( t 0:, 6 $$ /54054 t 0,: t 0(: 6 $$ 6 6 $$ 6 $$ 6 $$ 6 $$ 6 $$ 6 6 $$
package information 54AC164245 18/22 doc id 18093 rev 2 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark.
54AC164245 package information doc id 18093 rev 2 19/22 figure 8. flat-48 package mechanical drawing note: the upper metallic lid is not electrically conne cted to any pins, nor to the ic die inside the package. connecting any unused pins or the metal lid to ground or to the power supply will not affect the electrical characteristics. table 9. flat-48 mechanical data dim mm inch typ min max typ min max a 2.47 2.18 2.72 0.097 0.086 0.107 b 0.254 0.20 0.30 0.010 0.008 0.012 c 0.15 0.12 0.18 0.006 0.005 0.007 d 15.75 15.57 15.92 0.620 0.613 0.627 e 9.65 9.52 9.78 0.380 0.375 0.385 e2 6.35 6.22 6.48 0.250 0.245 0.255 e3 1.65 1.52 1.78 0.065 0.060 0.070 e 0.635 0.025 f0.20 0.008 l 8.38 6.85 9.40 0.330 0.270 0.370 q 0.79 0.66 0.92 0.031 0.026 0.036 s1 0.43 0.25 0.61 0.017 0.010 0.024
ordering information 54AC164245 20/22 doc id 18093 rev 2 7 ordering information table 10. order codes order code description temperature range package marking packing rhrac164245k1 engineering model -55 c to +125 c flat-48 rhfac164245k1 conductive strip pack rhrac164245k01v qmlv- flight 5962r9858008vyc
54AC164245 revision history doc id 18093 rev 2 21/22 8 revision history table 11. document revision history date revision changes 23-sep-2011 1 initial release. 06-apr-2012 2 added pin 4 description to table 3: pin descriptions .
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